Semiconductor Engineering

Understanding UVM Coverage For RISC-V Processor Designs

This white paper focuses on the first technique in this list. It explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification ...
Semiconductor Engineering

Inside UVM

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...
Design And Reuse

DDR Verification Challenges in Modern Chip Design

That’s the reality of modern DDR verification. Double Data Rate (DDR) memory interfaces are fundamental to modern SoC and ASIC designs, enabling high-bandwidth communication between processors and ...
EDN

The pitfalls of mixing formal and simulation: Where trouble starts

The most effective functional verification environments employ multiple analysis technologies, where the strengths of each are combined to reinforce each other to help ensure that the device under ...